Modern integrated circuits include many modules that may require different clock signals. Many clock signals can be generated by dividing an input clock signal by a clock divider in order to provide a lower frequency clock signal. Some clock dividers should also be adapted to provide a non-divided version of an input clock signal.
In order to simplify the design of modules that are connected to the clock divider the provision of the non-divided version of the input clock and any divided version of the input clock signal should be characterized by the same delay period.
FIG. 1 illustrates prior art clock divider 10. Prior art clock divider 10 includes clock divider 20, bypass path 30 and selection circuit 40. Bypass path 30 includes a sequence of delay units such as inverters 32. Clock divider 20 includes a sequence of flip-flops 22 and combinational logic 24 that form a counter.
Clock divider 20 and bypass path 30 receive an input clock signal clkin 200. Clock divider 20 divides clkin 200 by a division ratio that differs from one. Bypass path 30 provides a delayed version of clkin 200.
Selection logic 40 outputs an output clock signal (either the delayed version of clkin 200 or a divided clock signal) to module 50.
Bypass path 30 and clock divider 20 can introduce the same delay over a very narrow temperature range, a very narrow voltage supply range and over a narrow process variation window.
In most cases bypass path 30 and clock divider 20 introduce different delays and the difference between these delays can be hard to predict. The delay difference can affect the manner in which module 50 operates.